Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multi-level interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio openings, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features in multi-level IC semiconductor devices. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron and nanometer dimensions the capacitance of the various levels of the multi-level IC device becomes more critical, high capacitances lowering signal transport speed. Related to the capacitance of a particular level of a multi-level IC device are the dielectric constants of the various dielectric layers. In addition parasitic capacitances can be added by metal filled features that are adjacent to one another. In this respect, as critical dimensions have been reduced to sub-quarter micron, and more recently less than about 0.1 micron, low-K (low dielectric constant) dielectric insulating layers, for example having a dielectric constant of less than about 3.0, are required to achieve acceptable signal transport speeds.
The use of copper to decreases IC wiring resistances and the use of low-K materials, has contributed to new challenges in IC device manufacturing. For example, CMP planarization of copper filled features, in conjunction with low-K material layers leads to preferential polishing rates depending on the density of the patterned copper features present in a particular area of the process wafer surface. For example, a high feature pattern density portion of a process wafer surface tends to polish faster than a relatively lower feature pattern density portion leading to irregularities in surface topography. Such surface irregularities can adversely affect subsequent processes, leading to IC wiring failures and defects.
While the addition of dummy metal filled features to equalize pattern densities and therefore CMP polishing rates across the process wafer surface have been proposed in the prior art, such dummy metal filled features have the offsetting shortcoming of increasing the capacitance of a particular layer in a multi-level IC device. Increased capacitances can degrade IC device performance by slowing signal transport speeds, which is especially detrimental to high speed IC devices.
There is therefore a need in the integrated circuit processing art to develop a method of improving the uniformity of polishing in CMP processes while avoiding increased capacitance in multi-level IC semiconductor devices.
It is therefore an object of the invention to provide a method of improving the uniformity of polishing in CMP processes while avoiding increased capacitance in multi-level IC semiconductor devices, in addition to overcoming other shortcomings and deficiencies in the prior art.